The present invention generally relates to semiconductor devices and more particularly to forming n-type field effect transistor (n-FET) devices having reduced gate resistance.
Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FET) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. Most common among these may be metal-oxide-semiconductor field effect transistors (MOSFET), in which a gate structure may be energized to create an electric field in an underlying channel region of a semiconductor substrate, by which charge carriers are allowed to travel through the channel region between a source region and a drain region of the semiconductor substrate. The gate structure may be formed above the channel region and may generally include a gate dielectric layer as a part of or underneath other gate elements. The gate dielectric layer may include an insulator material, which may prevent leakage currents from flowing into the channel region when a voltage is applied to a gate electrode, while allowing the applied voltage to set up a transverse electric field in the channel region in a controllable manner.
In a replacement metal gate (RMG) fabrication approach, a dummy gate may be formed in the semiconductor substrate. The dummy gate may be patterned and etched from a polysilicon layer above the semiconductor substrate. In fin field effect transistor (FinFET) devices, the dummy gate may be formed over a portion of one or more fins formed from the semiconductor substrate. In some cases, the dummy gate may be formed surrounding a nanowire or above a semiconductor-on-insulator (SOI) substrate. Gate spacers may be formed on opposite sidewalls of the dummy gate. The dummy gate and the gate spacers may then be surrounded by an interlevel dielectric (ILD) layer. Later, the dummy gate may be removed from between the gate spacers, as by, for example, etch processes such as reactive ion etch (RIE) or wet etch chemistry. This may create a trench between the gate spacers where a metal gate, or gate electrode, may then be formed. One or more gate dielectric layers may be generally configured below the metal gate, where numerous layers of workfunction metals may be generally formed. Then, a low resistive metal may be deposited as a gate electrode to fill a remaining portion of the trench. This sequence of layers including the gate dielectric layers, the workfunction metals and the low resistive electrode metal may be referred to as a metal gate stack.